This invention relates to the fabrication of three-dimensional electronic packages in which a multiplicity of individual integrated circuit (IC) chips are secured together in a stack which provides a very high density electronic package.
As stated in common assignee U.S. Pat. No. 5.279.991, issued Jan. 18, 1994, which provides more detailed disclosure of certain process steps, the assignee of this application pioneered the use of IC chip stacks, first as modules providing photo-detector focal plane circuitry, and then as units suitable for computer memories and the like. U.S. Pat. Nos. 4,525,921 and 4,646,128 relate to the stacks designed for general use as memory devices and other non-focal-plane packages.
The methods used for fabricating such three dimensional (3D) IC chip stacks have become increasingly sophisticated. The three dimensional approach has been applied to both SRAM and DRAM memory chips with satisfactory results. Stacking of memory chips has reached density levels of seventy chips in a 0.220 inch.times.0.520 inch.times.0.520 inch stack, each chip having a 1 megabit memory. In addition to memory chips, various other types of IC chips may be stacked in 3-D packages.
One problem, which applies to stacks used as memory devices and also to other non-focal-plane packages, is the difficulty of connecting exterior circuitry to the large number of conductors on the access plane of the completed stack. Focal plane chip stack modules incorporate multiplexer circuitry, which greatly reduces the number of module output connections. However, providing output connections for memory devices, and offer non-multiplexed devices, is a much greater challenge.
There are two acknowledged orientations which represent the structural relationship of the stacked IC chips in a module to the lead-out plate, or substrate, which makes outside electrical circuitry available for connection to the multiplicity of electrical leads (terminals) which are formed on the access plane face of the module, and which lead to the IC circuitry embedded in the module. In one arrangement, the layers of the module extend in planes perpendicular to the plane of the lead-out plate, or substrate. And in the other arrangement, the layers of the module extend in planes parallel to the plane of the lead-out plate, or substrate.
The lead-out plates, or substrates, may be located below, above, or along the side of, the stacked chip module. The two most common structures are described as a "sliced bread" stack, or as a "pancake" stack. Common assignee U.S. Pat. No. 4,706,166 discloses a "sliced bread" stack, in which the IC chips in the stacked module are in planes perpendicular to a stack-supporting substrate. The substrate carries electrical conductors, which lead to external circuitry. The access plane of the stack faces the supporting substrate. And the electrical connections between the stack face and substrate are formed by bonding aligned solder bumps on the facing surfaces, a process which may be referred to as surface mount technology. In such a construction, the lead-out terminals are necessarily located very close to one another, a fact which creates difficulties in obtaining satisfactory lead-out connections.
"Pancake" stacks comprise IC chips which are in planes parallel to a supporting substrate. The electrical leads from the many terminals on the access plane of the stack preferably are brought either to the bottom or to the top of the stack, in order to be connected to external circuitry. Such "pancake" stacks are disclosed in copending common assignee U.S. Pat. No. 5,279,991. "Pancake" stacks, as distinguished from "sliced bread" stacks, are more likely to be used where a smaller number of IC chips are included in the stacked layer module, either because fewer chips are needed for a particular module, or because of limited "headroom" i e limited available space in which the module is located.
The present invention deals primarily with the problem of connecting the circuitry of IC chips in pancake stacks with suitable lead-out terminals, which are then used in connecting to external circuitry.